1. Field
An aspect of the present inventive concepts herein relates to a method of manufacturing a semiconductor device having a doped layer comprising at least one of n-type and p-type impurities. The n-type or p-type impurities may be diffused into a gate electrode layer by performing an additional process, e.g., a heat treatment process.
2. Description of the Related Art
Responding to the growing demands for miniaturization of a semiconductor device, conductive lines, e.g., word lines or bit lines, formed in the semiconductor device have been downsized and the space between the conductive lines has been narrowed. Thus, a parasitic capacitance may increase between the conductive lines.
In order to reduce the parasitic capacitance, research activities have been focused on reducing the thickness of the gate electrode layer, which is formed on a gate dielectric layer and forms a portion of the word lines. However, if the thickness of the gate electrode layer is thinner than a certain thickness, it may cause some problems when injecting n-type or p-type impurities into the gate electrode layer by using an ion implantation process.
Specifically, if the thickness of the gate electrode layer is thinner than a certain thickness, it may be very difficult to control the distribution and/or the injection depth of the impurities, which are injected by the ion implantation process, in the gate electrode layer. The reliability of the gate dielectric layer also may be degraded because relatively more impurities may be injected into the gate dielectric layer through the gate electrode layer. If the energy of the ion implantation process is reduced to control the distribution and the injection depth of the impurities, process time of the ion implantation process may be prolonged, thereby hampering productivity.